1. Field of the Invention
The present invention is directed to providing a digital filter and modulator. The invention is further directed to providing cost effective structural and procedural approaches to employ channelization filtering and efficiently applying modulation such that throughput delay can be minimized.
2. Description of Related Art
Now that digital systems are being used in the radio frequency (RF) region, such as, for electronic warfare (EW) applications, a low-power source for all RF signals has been developed known as the coherent digital excitor (CODE) device. One of the most important functions of the CODE device is the ability to apply programmable distinctive modulation on a programmable frequency selective basis throughout the radar band spectrum. The modulation functions include amplitude, phase, frequency (offset), and delay range or time. The programmable frequency selectivity is accomplished with a bank of programmable filters, i.e., channelization. Each received signal passes down one and only one of the channels, allowing distinctive modulation to be applied in each channel.
FIG. 1a shows a generic structure 10 for digital filters. This structure 10 consists of a combination of delay elements 12, adders 14 and multipliers 16. The delay elements 12 are positioned between adders 14. In the generic structure shown, the multipliers 16 form both a feed forward path 18 and a feedback path 20.
In the feed forward path 18, the input signal is delivered to a plurality of multipliers 16, where the input signal is multiplied by a weight. The input signal is also delivered to a delay element 12, and then to an adder 14, which outputs the sum of the weighted signal and the delayed signal.
In the feedback path 20, the output signal is delivered to another plurality of multipliers 16, where the output signal is multiplied by a weight. The weighted output signal is then delivered to an adder 14, which outputs the sum of the weighted signal and the delayed signal.
One common type of digital filter which uses the generic structure shown in FIG. 1a is a finite-impulse-response (FIR) filter, shown in FIG. 1b.
The FIR filter only used the feed forward path 18 shown in FIG. 1a. The delay elements 12 are replaced with a digital tapped delay line 22. This results in a moving average which is non-recursive.
For typical electronic warfare (EW) applications, the FIR filter will be designed with 30 to 40 taps. The FIR filter is programmed, i.e., appropriately and individually adjusting the weights of these taps. This programming involves controlling the three key filter parameters, i.e., the center frequency, the bandwidth, and the shape factor.
However, there appears to be a potential fundamental compatibility problem when used with a digital modulator. Even though the straight through gain requirement is nominally unity, some of the adds of FIG. 1b, prior to the final add, would overflow, thereby giving an "illegal" output. This problem has led to research to develop alternatives when the filter is to be used with such digital modulators, which are the subject of the present application.
There are two difficulties with the FIR digital filter design mentioned above. First, there is great incentive to increase the processing clock rate so that the radar bands can be covered (e.g., by the EW equipment) in as cost effective manner as possible. The FIR digital filter design appears compatible with acceptably significant clock rates, in the order of 200 megahertz to 400 megahertz, when properly integrated with application specific integrated circuits (ASICs).
However, the interfacing digital modulators cannot support such a high clock rate. As one important example, there is a high quality very dense digital memory available, which is needed for the range delay modulation, where a high clock rate is not compatible with its interface or with its efficient use in terms of size per microsecond of memory. The other digital modulating processing circuits have clock rate compatibility problems also.
The second motivation in seeking alternative designs is to reduce cost and size. Although the FIR mentioned above is more economical than the analog circuits it is intended to replace, it is still desirable to reduce the cost and size even more.